Development of a novel fault-tolerant reduced device count T-type multilevel inverter topology

Abstract

Multilevel inverters (MLIs) are emerging topologies in medium and high power applications due to low total harmonic distortion (THD) and reduced voltage stress across switches. The reliability of semiconductor devices is a major concern for these multilevel inverter topologies to function properly. Therefore, a reliable single-phase fault-tolerant (SPFT) T-type 5-level multilevel inverter topology is presented in this paper. The proposed T-type topology can tolerate Open Circuit (OC)fault, either caused by a failure of anyone single switch or/and the failure of anyone leg of the H-bridge. The proposed configuration is not only fault-tolerant but also reliable due to the reduced number of switching devices as compared to the conventional T-type multilevel inverters. Moreover, the proposed T-type topology inherently achieves self-voltage balance in DC-Link capacitors. The proposed T-type topology is simulated in MATLAB/Simulink environment and results are discussed for normal (pre-fault), faulty and post-fault conditions. Experimental results validate the robustness and effectiveness of the proposed T-type topology to tolerate OC faults across the switch(es). Moreover, simulation and experimental results establish that proposed T-type topology significantly increase the reliability of the multilevel inverter. Furthermore, comprehensive analysis is presented to show the superiority of the proposed T-type topology over the recently proposed fault-tolerant topologies.