Abstract

The through-Silicon-Vias (TSV) is a key component of three dimensional electronic packaging, knowing its stresses is very important for its reliability evaluation. In this paper, we evaluated the stress of TSV during thermal cycling with a micro-infrared photoelasticity system in full field and real time measurement mode, three important findings are reported. First, it was found that electroplating was a source of residual stress of TSV, and although annealing was helpful to release the chemical stress, it may cause thermal stress as well; Second, TSV obtained and kept its stress-free state as temperature is above 180–200° C; Third, with the increase of thermal cycling, residual stress of TSV tended to increase as well but got stabled when the number of thermal cycling is high enough. Besides, this paper reports experimental evidence of interfacial sliding between Cu and Si in Cu-filled TSVs during thermal loading/cycling, which be used to illustrate the above findings.

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