Developed configuration of stacked multicell topology with reduced DC voltage sources

Abstract

SummaryMultilevel inverters are considered as a suitable alternative for the two‐level topology in the medium‐voltage, high‐power applications because of the higher number of voltage levels, and, as a result, reduced harmonic distortion. One of the most critical types of multilevel inverters is the flying capacitor topology, in which the stacked multicell topology is derived from this type of multilevel inverters. This paper presents a developed configuration of the stacked multicell topology, constructed from 2m × n primary commutation cells, which generates the output voltage of (2m × n)+1 levels. The most crucial point in the flying capacitor‐based topologies is balancing the flying capacitors' voltages, which is the primary condition of these topologies' correct operation. Also, in this topology, the number of required DC voltage sources is decreased compared to the existing multicell topology. Moreover, the developed topology can generate a higher number of voltage levels without cascading several cells. The developed multicell inverter topology is controlled based on the disposition band carrier and phase‐shifted carrier sinusoidal pulse width modulation (DBC‐PSC‐SPWM) method. Because of this control method, the voltages of capacitors are self‐adjusted at their value. The proposed topology is simulated in different conditions using PSCAD/EMTDC software and to show the validity of the proposed topology and the control method, and simulation results are demonstrated. A laboratory‐type experimental setup is used to validate the modulation strategy and other findings.