Deterministic BIST based on a reconfigurable interconnection network

Abstract

We present a new approach for deterministic BIST in which a reconfigurable interconnection network (RIN) is placed between the outputs of a pseudo-random pattern genera- tor and the scan inputs of the circuit under test (CUT). The RIN, which consists only of multiplexer switches, replaces the phase shifter that is typically used in pseudo-random BIST to reduce correlation between the test data bits that are fed into the scan chains. The connections between the LFSR and the scan chains can be dynamically changed (reconfigured) during a test session. In this way, the RIN is used to match the LFSR outputs to the test cubes in a deterministic test set. The control data bits used for re- configuration ensure that all the deterministic test cubes are em- bedded in the test patterns applied to the CUT. The proposed ap- proach requires very little hardware overhead, and fewer control bits compared to the storage required for reseeding techniques or for hybrid BIST. Moreover, as a non-intrusive BIST solution, it does not require any circuit redesign and has minimal impact on circuit performance.