Determining the Surface Electrostatic Potential Ψ s of a Dielectric-Bordering Semiconductor Using the Method of Ψ s " /Ψ s Diagrams

Abstract

A quantitative approach to determining the integration constant Ψs0(Vg0) in an expression relating the semiconductor surface potential Ψs to the voltage Vg applied to the metal–insulator–semiconductor (MIS) structure and its quasi-static capacitance–voltage characteristic Cv(Vg) (normalized to the “dielectric capacitance”) is described. The method is based on the analysis of experimental functions Ψs"(Ψs), where Ψs" = dΨs/dVg, and the same functions calculated for an ideal MIS structure. The obtained function Ψs(Vg) is a rather exact and complete characteristic of electron properties of the MIS-structure phase boundary (the integrated interface state density, flat-band voltage VFB, sign and density of the dielectric fixed charge, and variations of these parameters under the action of various factors). Using the example of a particular n-Si MIS structure, it is shown that the method of Ψs"/Ψs diagrams ensures a noticeable (up to ≅0.93 eV) widening of the Si gap sounding region and observation (by the value of the VFB shift) of very small (∼ 1 × 107 cm–2) variations in the charge density at the Si/SiO2 phase boundary.