Abstract
A modification of the programmable logic array (PLA), whose operation is controlled by a clock signal, is suggested. The problem of determination of the time delay of such PLA is treated. The time delay is determined by simulating the circuit-design description of the PLA represented as a network of constituent transistors. The circuit-design description is generated on the basis of the logic description of a set of Boolean functions implemented with the PLA. To reduce the time of simulation, the method of minimization of the number of test vectors is suggested.
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