Detection of false paths in logical circuits by joint analysis of the AND/OR trees and SSBDD-graphs

Abstract

Consideration was given to the problem of time verification of the combinational circuits, namely, to the problem of determining the false paths. The delays arising in the false paths do not manifest themselves in the circuit operational mode. At determination of the maximal circuit delay as a whole it is recommendable to detect and disregard such paths. It was proposed to reduce the problem of detecting a false path to the search of a test pattern for the stuck-at 0.1 faults of the character of the equivalent normal form corresponding to this path. Search of the test patterns comes to analyzing the conjunctions of the equivalent normal form represented compactly by the AND-OR trees and the structurally synthesized binary decision diagrams. The joint analysis of the AND-OR trees and such diagrams was oriented to reducing the computer burden at seeking the test patterns.