Detection of CMOS address decoder open faults with March and pseudo random memory tests

Abstract

A new method to integrate a test for CMOS address decoder open faults into March and pseudo random tests employed for testing semiconductor memories is presented. For commonly used memory organizations, March tests are implemented that, in addition to their original target faults, detect all CMOS address decoder open faults. The defection of these faults has been believed to require separate deterministic test patterns or tests of higher order. Address sequences generated by special complete LFSRs and address dependent data are utilized to alter March tests to detect all address decoder open faults and retain the detection properties of the original tests. The additional overhead in terms of silicon area for an on-chip realization of a built-in March test with the added fault detection features is negligible, and the test application time remains of O(N).