Detection and Evaluation of Deterministic Jitter Causes in CP-PLL?s Due to Macro Level Faults and Pre-Detection Using Simple Methods

Abstract

Charge-Pump Phase-locked loops are currently used in a variety of SoC signal generation applications. They ultimately determine performance of other SoC blocks, such as ADC’s, DAC’s, RF and synchronisation functions. In many situations, only simple frequency lock tests are carried out on the CP-PLL portion of a circuit, with other complex direct jitter tests being carried out indirectly at a higher system level. Although these higher level system tests must generally be carried out at some point they can be time consuming. In addition, if the PLL is designed and operating correctly the PLL system will generally have far better performance than the system it is driving. This paper investigates typical jitter output responses of CP-PLLs when subjected to selected forward path leakage faults. The evaluation platform consists of a macro level mixed signal based PLL-Model. Degradation of the PLL output is evaluated from the phase noise spectrum, jitter spectrum and sideband spur degradation. Further evaluations and analysis are supplied relating block level effects to jitter and phase noise. Investigations are made as to the efficacy of detection of these errors with simple measurement techniques. The crux of the work is thus initially to develop techniques to aid evaluation of the likely jitter performance of a CP-PLL system without resorting to direct measurement techniques.