Detect DRAM Disturbance Error by Using Disturbance Bin Counters

Abstract

DRAM disturbance errors are increasingly a concern to computer system reliability and security. There have been a number of designs to detect and prevent them; however, there lacks any design that guarantees 100 percent detection (no false negative) with a small and fixed hardware cost. This paper presents such a design based on a novel idea called disturbance bin counter (DBC). Each DBC is a complex counter that maintains an upper bound of disturbances for a bin of DRAM rows. Their access is not in the critical path of processor execution and thus incurs no performance overhead. The design is optimized at the circuit level to minimize the storage requirement. Our simulation results using multi-core SPEC CPU2006 workloads show that no false positive occurs with a 1,024-entry DBC table, which requires only 4.5 KB storage. The design can be incorporated into a memory controller to guarantee the detection of DRAM disturbance errors or row hammering by malicious programs.