Design-overlay interactions in metal double patterning

Abstract

In double patterning lithography (DPL), overlay error between two patterning steps at the same layer translates into CD variability. Since CD uniformity budget is very tight, overlay control becomes a tough challenge for DPL. In this paper, we electrically evaluate overlay error for BEOL DPL with the goal of studying relative effects of different overlay sources and interactions of overlay control with design parameters. Experimental results show the following: (a) overlay electrical impact is not significant in case of positive-tone DPL (< 3.4% average capacitance variation) and should be the base for determining overlay budget requirement; (b) when considering congestion, overlay electrical impact reduces in positivetone DPL; (c) Design For Manufacturability (DFM) techniques like wire spreading can have a large effect on overlay electrical impact (20% increase of spacing can reduce capacitance variation by 22%); (d) translation overlay has the largest electrical impact compared to other overlay sources; and (e) overlay in y direction (x for horizontal metalization) has negligible electrical impact and, therefore, preferred routing direction should be taken into account for overlay sampling and alignment strategies.