Abstract

The frozen set selection of polar codes, known as bit selection, determines the error-correcting performance of polar codes. The original bit selection was derived for successive cancellation decoding in a binary erasure channel. Density evolution has been used to evaluate the bit error probability in binary memoryless channel, but the computational complexity is still high and the simplified versions rely on different degrees of approximations. We propose an alternative simulation-based in-order bit selection method that evaluates the error rate of each bit using Monte Carlo decoding simulations and selects the frozen set based on the bit reliability ranking. The simulation-based method does not rely on channel models and it can be applied to any practical channels in the field. The simulation can be accelerated on an FPGA platform to significantly shorten the time required to one day for a 1024-b code design. We use three examples to demonstrate the in-order bit selection method, a (256, 128) code, a (512, 256) code, and a (1024, 512) code. Compared with the codes designed using density evolution for an AWGN channel, our (256, 128) code shows a competitive BER; our (512, 256) code outperforms at low SNR; and our (1024, 512) code outperforms across a wide range of SNR by 0.3 to 0.6 dB. The algorithm and methodology are applicable to any code rate and longer code lengths.

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