Designing LDPC system using prob domain decoder in Xilinx system generator

Abstract

Low-Density Parity-Check (LDPC) code represents a type of Forward Error Correction (FEC) codes, it is a very perfect code with the ability to correct the errors and it has a performance in term of Bit Error Rate (BER) close to Shannon limits. As this code has many features like reliability, flexibility in implementation and a facility of adaptation. So it takes place in the current area of 4G and even 5G network communications. In this paper, an efficient and optimum design for LDPC system using prob domain decoder is implemented using a Xilinx system generator to evaluate its performance in terms of BER, its complexity and the time needed. FPGA device Kintex7 (XC7K325T-2FFG900C) is used for the implementation of the proposed model. The results show that by increasing the Signal to Noise Ratio (SNR), the values of the BER will be improved significantly.