Designing Data-Aware Network-on-Chip for Performance

Abstract

Network-on-Chip (NoC) is a widely adopted communication infrastructure in Tiled Chip Multi-Processors (TCMPs) due to its high transfer bandwidth, scalability and reliability. As the number of cores continues to increase in modern TCMPs, NoC plays a pivotal role in determining the performance. In fact, it is reported that NoC is responsible for 60 % to 75% of the miss latency experienced by the applications run on TCMPs. Nevertheless, most of the existing memory access techniques and optimisations are NoC oblivious, which limits their performance. This work advocates for considering NoC and memory hierarchy together when designing techniques and proposing optimisations for TCMPs. It shows that designing data-aware NoC with the help of memory hierarchy improves resource utilisation, reduces memory access latency and improves system performance. Specifically, the architectures proposed in this work can improve overall system performance by up to 19 % with negligible storage, area and power overhead. While TCMPs continue to scale with the help of electrical, wireless and photonic NoCs, the proposed work can influence future design decisions.