Abstract
With the increase of transistors' density, popularity of System on Chip (SoC) has increased exponentially. As a communication module for SoC, Network on Chip (NoC) framework has been adapted as its backbone. In this paper, we propose a methodology for designing area-optimized application specific NoC while providing hard Quality of Service (QoS) guarantees for real time flows. The novelty of the proposed system lies in derivation of a Mixed Integer Linear Programming model which is then used to generate a resource optimal Network on Chip (NoC) topology and architecture while considering traffic and QoS requirements. We also present the micro-architectural design features used for enabling traffic and latency guarantees and discuss how the solution adapts for dynamic variations in the application traffic. The paper highlights the effectiveness of proposed method by generating resource efficient NoC solutions for both industrial and benchmark applications. The area-optimized results are generated in few seconds by proposed technique, without resorting to heuristics, even for an application with 48 traffic flows.
Highlights
As CMOS technologies have scaled down, increasingly large system-on-chip (SoC) designs are being manufactured today
In this work we propose a methodology for designing optimized application specific network-on-chip topologies and generating efficient architectures while meeting hard Quality of Service (QoS) requirements of the application simultaneously
The second is a multimedia SoC design with over 50 masters/slaves [5]; for the topology generation we target the backplane with 12 master and 4 slaves to a total of 21 flows, of which four flows are priority flows for which we convert latency guarantees from hopcounts to time units
Summary
As CMOS technologies have scaled down, increasingly large system-on-chip (SoC) designs are being manufactured today. Torus) for the NoC architecture and use some form of resource reservation to meet the traffic and latency requirements of the application These topologies may not necessarily be optimized for cost and the manual specification of the topology may require extra effort. In this work we propose a methodology for designing optimized application specific network-on-chip topologies and generating efficient architectures while meeting hard QoS requirements of the application simultaneously. The proposed system presents a mathematical model which generates an area-optimized network-on-chip topology given a set of bandwidth and QoS of the application. We present micro-architectural techniques on how proposed system incorporates QoS in the network-on-chip while efficiently utilizing hardware resources and keeping the solution flexible for dynamic traffic variations.
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