Designing a STT-MTJ 2:1 multiplexer in 45 nm technology node

Abstract

Magnetic tunnel junction (MTJ) is one of the spintronic effects and in front of complementary metal oxide semiconductor (CMOS) technology. This element is capable of performing logical calculations and storing the output data in itself, therefore, the day by day use of it makes it more extensive in combination with CMOS as well as its reduction in designing logical, programmable and memory circuits and gates, with higher performance speed, non-volatile (NV) and high stability. Thus, in recent studies, spin transfer torque (STT) based CMOS/MTJ circuits were designed to further reduce power consumption and time delay. In this paper, a 2:1 multiplexer with change and reform in the previous circuits is presented. In proposed circuit there is not the problem of data missing in Simultaneous state change of select signal (S) with clock pulse (Clk) (or close to S with Clk). In proposed design effective area and control speed is optimized by change in writing control circuit. The simulation results revealed that power delay product (PDP) is decreased by 53.44% when compared with that of the previous circuit. Simulation is done by standard CMOS model under 45 nm technology using HSPICE simulator.