Abstract
A framework for prediction and estimation of the test yield and test cost of VLSI systems during the design-for-testability stage is given. As an important extension, the authors present a technique for evaluating the set of possible solutions and selecting the most effective one. This technique is based on the evaluation of test-related performance measures and on decision theory. As a result, a new level of design and test integration is obtained. Experimental results have confirmed the applicability and effectiveness of the method. It is shown that it is possible to derive, in a very straightforward manner, maximum and minimum expected values of the design yields of a strategy (design scheme). >
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