Design voltage comparator 14-bit for successive approximation analog-to-digital converter

Abstract

A comparator plays a significant role in the developing of ADC. This comparator aims to get small offset value for high resolution. Several architectures present to optimize the offset voltage. The comparator designed for a 14-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). The main advantage of the implemented comparator of SAR ADC, which is the right choice for high resolution. This schematic design and layout simulation have implemented in Silterra C18G process 0.18um CMOS Technology by using Synopsys EDA Tools with transient and Monte Carlo. A double tail regenerative comparator is studied and investigated during this project. The simulation results complete with a 3.3V power supply. This comparator operates in 5MHz clock frequency with offset voltage for the latch is 32mV.