Design, Verification and Testing of Comprehensive Serial Peripheral Interface

Abstract

Synchronous serial interfaces are frequently employed to offer cost-effective board-level interfaces between various devices, including microcontrollers, DACs, ADCs, and others. Components that are compatible with SPI and Microwire are made by numerous IC makers. An interface called Serial Peripheral Interface (SPI) makes it easier to send synchronous serial data. In master/slave mode, data frames are initiated by the master device. With a separate slave choose line, multiple slave devices are permitted. It is necessary to guarantee that the given hardware design operates as intended and produces the desired outcomes. The design phases would need to be repeated after the functional flaws were discovered. Verification is thus a process that is time and money efficient. Due to this, a strong testbench structure is required, one that includes large broad verification elements that are easily extensible across designs and are extensively reusable. To gain good control over stimulus creation, functional coverage, and other factors, an industry standard verification technique is needed. The primary goal of this work is to design the Master SPI Core and use System Verilog to validate the code. Serial Peripheral Interface of symmetrical structure was synthesized using Cadence genus, and then simulated using Questa IDE. The testing of the SPI core was done by inserting the scan chains using the Cadence Genus tool and finally the code coverage of the SPI core was captured using the Questa IDE. Keywords: SPI, Coverage, Protocol, I2C, Functional Verification