Abstract

Injection-locked frequency divider (ILFD) is an essential component of a phase-locked loop (PLL) used in a communication transceiver. Due to the rapid growth of virtual reality and artificial intelligence technologies, high-speed communication has become a crucial factor. As a result, highly efficient ILFDs must be engineered to ensure accurate high-speed communication. An optimized ILFD is anticipated to have a large locking range, a low power consumption, a low phase noise, and a low injection power for better functioning of a high speed PLL. However, there are inevitable trade-offs of frequency, phase noise, division ratio, and power consumption, making it more challenging to design an ILFD with a high division ratio at higher frequencies. Choosing an appropriate topology for different operational frequencies is also a challenging task for RFIC designers. This study exemplified different design architectures available for CMOS ILFDs in different super high frequency (SHF) and extremely high frequency (EHF) frequency ranges. The performance parameters of these architectures are analyzed, and a detailed discussion on the device’s performance is presented. This review will serve as a comparative study and reference for the RFIC designer’s future ILFD designs.

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