Design Tradeoffs for a CT-ΔΣ ADC With Hybrid Active–Passive Filter and FIR DAC in 40-nm CMOS

Abstract

This letter analyzes the constraints and tradeoffs involved in the design of a third-order single-bit quantizer-based continuous-time delta–sigma modulator (CTDSM) with a hybrid active–passive loop filter. The jitter suppression capability of an FIR DAC is combined with the superior out-of-band quantization noise filtering capability of a passive filter, thereby enabling the use of an energy-efficient Gm-C integrator at the front-end. Nearly 60 percent of the dc loop gain is derived from the single-bit quantizer, thus greatly relaxing the dc gain requirement for the active integrators. We also analyze the modulator’s stability for an input signal near full scale. Fabricated in a 40-nm CMOS, the prototype CTDSM occupies a core area of 0.034 mm2 and achieves SNDR, SNR, and DR of 65.6 dB, 66.7 dB, and 67.3 dB, respectively, in a 5-MHz bandwidth at 1 GS/s.