Design Trade-offs and Considerations for Improving the PCB Current Carrying Capacity in High Power Density Power Electronics Applications

Abstract

This paper investigates printed circuit board (PCB) design trade-offs and considerations to maximize the current carrying capacity of traces in PCB-based power electronics applications. Many existing designs rely on methodologies through empirical data presented by the outdated IPC-2152 standard. A design methodology to maximize the utilized PCB area and improve thermal performance is introduced. To assess this methodology, lumped parameter (LP) and finite element (FE) models are developed and computational fluid dynamics (CFD) simulations are carried out. Thermal via placement strategies are investigated and maximum allowable power dissipation on the PCB traces is calculated. Simulations and analyses are experimentally validated on a PCB-based 100kW three-phase three-level inverter. The that results show that the thermal and electrical models discussed in this paper have superior accuracy compared to traditional formulations.