Abstract
LDMOS devices with grounded gate shield structures variations were simulated and tested, aiming to address hot carrier immunity and robustness concurrently. Optimal configuration of grounded gate shield structure was found to reduce local electrical field strength at gate-to-drain overlap for better hot carrier immunity, and to achieve uniform E-field distribution on drain side for robustness as well. Design trade off of hot carrier immunity (HCI) and robustness is analyzed by simulation and silicon data.
Highlights
Research on hot carrier immunity (HCI) were forces on improving the silicon oxide interface quality and reducing the impact ionization near the interface [1]
Robustness of LDMOS can be correlated to the inherently present parasitic bipolar NPN transistor [7], and more body doping to reduce body resistance was suggested. e device could fail because of formation of early lament [8, 9], deep implant drain [10], and ESD implant at drain side [11] were suggested to address the formation of early lament issue. ese techniques modify the electric eld distribution at the channel and dri region, and have e ect on hot carrier injection
It can be summarized that devices with longer shield have less impact ionization and lower electric eld near the gate, which may resultings in better hot carrier immunity, but higher electric eld distribution near the drain may results in worse robustness. is can be explained as the electric eld distribution changed by the longer part of shield
Summary
Research on HCI were forces on improving the silicon oxide interface quality and reducing the impact ionization near the interface [1]. Impact ionization and electric eld distribution at the dri region near the gate of di erent shield structures are simulated to evaluate the HCI reliability. Power from output mismatch will re ect to the LDMOS drain, resultings in high drain voltage and strong electric eld at the dri region. Trigger parasitic NPN transistor, causing the formation of early lament [8, 9], and failure of device During this power discharging process, the highest electric eld happens at the dri region near the drain because of kirk e ect [16]. To improve the robustness and HCI reliability, the electric eld of dri region near the drain and near the gate has to be designed carefully. For a device with given breakdown voltage, better electric eld distribution near the drain means worse near the gate and vice versa. is leads to a trade-o design in HCI reliability and robustness of LDMOS. e part will be TCAD simulation and observation of di erent con guration of gate shield
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