Abstract
Wireline transmitters operating at tens of gigabits per second pose challenging design issues ranging from limited bandwidths to severe sensitivity to jitter. This paper presents a number of analog and digital circuit techniques that allow data rates as high as 80 Gb/s in 45-nm CMOS technology. A PAM4 prototype delivers an output swing of 630 mV $_{pp}$ with a clock jitter of 205 fs $_{rms}$ while drawing 44 mW.
Highlights
W ITH the dramatic rise of data transport over the Internet, wireline systems are pressed for increasingly higher speeds
Wireline transceivers have been under intense development for two decades [1]–[17], inheriting broadband concepts from optical communication circuits as well as dealing with other issues that are related to copper media
The methods are introduced in the context of a 40-Gb/s TX [11] and an 80-Gb/s TX [10], which have been developed in 45-nm CMOS technology
Summary
W ITH the dramatic rise of data transport over the Internet, wireline systems are pressed for increasingly higher speeds. The low-frequency content (representing the “dc swings”) is attenuated This effect can be seen in the time-domain waveforms shown in Fig. 7(c): the output amplitude jumps to 1 + α immediately after a transition but drops to 1 − α for a consecutive sequence of ONEs or ZEROs. The swing reduction translates to additional challenges in receiver design. In addition to burning high power, such a current dictates large widths for M1 and M2, thereby introducing substantial capacitance at the input and output of the driver This issue in turn requires the use of various inductive and T-coil peaking techniques in both the stage preceding the driver and in the driver output nodes [21]. If Ron is a significant fraction of the back-termination resistance, its voltage dependence translates to nonlinearity
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