Abstract
This editorial examines design techniques for high-speed serial data links over wire channels. The state-of-theart of serial links over wire channels is briefly studied. The imperfections of wire channels at high frequencies and their effect on multi-Gbps serial links are examined. It is followed with a close examination of modulation schemes effective in combating the effect of the finite bandwidth of wire channels. Channel equalization, both pre-emphasis and post-equalization, are investigated with an emphasis on adaptive decision feedback equalization. Challenges and opportunities in combating ISI are explored.
Highlights
FT of MOS transistors has well exceeded 100 GHz, the speed of data links are rather low, as shown in Table 1 [1,2,3,4,5,6,7,8,9,10,11,12,13], mainly due to Inter-Symbol Interference (ISI) caused by channel imperfections including finite channel bandwidth, reflections, and cross-talks
This paper examines challenges encountered in and design techniques for multi-Gbps data communication over wire channels, and explores opportunities and solutions to improve the performance of data links
The remainder of the paper is organized as follows: Section 2 investigates the imperfections of wire channels and their impact on multi-Gbps data links
Summary
FT of MOS transistors has well exceeded 100 GHz, the speed of data links are rather low, as shown in Table 1 [1,2,3,4,5,6,7,8,9,10,11,12,13], mainly due to Inter-Symbol Interference (ISI) caused by channel imperfections including finite channel bandwidth, reflections, and cross-talks. This paper examines challenges encountered in and design techniques for multi-Gbps data communication over wire channels, and explores opportunities and solutions to improve the performance of data links. The remainder of the paper is organized as follows: Section 2 investigates the imperfections of wire channels and their impact on multi-Gbps data links.
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