Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection

Abstract

Error correction is an effective way to mitigate fault attacks in cryptographic hardware. It is also an effective solution to soft errors in deep sub-micron technologies. To this end, we present a systematic method for designing single error correcting (SEC) and double error detecting (DED) finite field (Galoisfield) multipliers over GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ). The detection and correction are done on-line. We use multiple Parity Predictions (PPs) to correct single errors based on the Hamming principles. Specifically, a structural approach is first presented. The predicted parities are derived from the input operands. Further, a hybrid approach is presented where the multipliers and PP circuits are synthesized, and the decoding and correction circuits are structurally combined to form the complete error correcting designs. Our technique, when compared with existing techniques, gives better performance. We show that our SEC multipliers over GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) require about 100% extra hardware, whereas with the traditional SEC techniques, such as the triple-modular redundancy (TMR), this figure is more than 200%.