Design-Stage Hardening of 65-nm CMOS Standard Cells Against Multiple Events

Abstract

We present a study on the layout design of the rad-hard standard logical cells and fault-tolerant static random access memory (SRAM) cells. We used the previously developed layout-aware SPICE-based simulation technique to check the design patterns that involve sensitive node spacing and contact placement to increase the tolerance to multiple node upsets. The results of the simulations were transformed into layout design recommendations verified by the simulation and experimental data for SRAM cells with layout design supporting the recommendations. The results proved the efficiency of the proposed hardening measures.