Design Space Exploration of HEVC RCL Mapped onto NoC-Based Embedded Platforms

Abstract

Nowadays, several applications running into embedded systems have to meet hard/soft real-time constraints. Generally, multimedia applications, like the modern High Efficiency Video Coding (HEVC) standard, present soft timing constraints. However, specific scenarios like robotic surgeries and coupling of satellites require hard real-time constraints, becoming a huge challenge. Although the implementation of such applications (or part of them) in Networks-on-Chip (NoC) and the use of hardware acceleration arise as alternatives to fulfill timing constraints, a design space exploration evaluating the NoC mapping and the hardware acceleration usage, with a schedulability analysis, is mandatory. In this work we perform a design space exploration of HEVC Residual Coding Loop (RCL) mapped onto a NoC-based embedded platform, combining traditional CPUs and hardware accelerators as processing elements (PEs). We considered the encoding of a single frame, with two different resolutions: 1920×1080 and 3840×2160 pixels, when running at CPUs and hardware accelerators, respectively. A set of analysis exploring the combination of different NoC configurations and task mapping strategies were performed, with the development of a search algorithm called SNFT (Schedulability breakdown NoC Frequency Tracking algorithm), as a way to find the minimum NoC frequency for each configuration which becomes the system fully schedulable, showing for the typical and upper-bound workload cases scenarios when the application is schedulable and meets the real-time constraints.