Design Space Exploration of Convolution Algorithms to Accelerate CNNs on FPGA

Abstract

Deep Neural Networks (DNN) are promising solutions for various artificial intelligence tasks. Convolutional Neural Network (CNN) is a variant of DNN, which is widely used in various computer vision tasks like image and face recognition, autonomous vehicles, games, video surveillance and various medical applications. CNNs are both compute and memory bound. Convolutional layers are the most computationally complex operation in CNN. Owing to the computation demanded by convolutions of CNNs, FPGAs are found to be suitable for accelerating CNNs. In this paper we have carried out a design space exploration of various algorithms for performing operations in different convolutional layers of CNNs. Analysis has been done to select an appropriate algorithm for various convolution layers of AlexNet CNN model based on the kernel size and input feature map. First convolution layer in AlexNet CNN model with three channels of $227 \times 227$ feature size and 96 channels of $11 \times 11$ kernel, has been implemented in Xilinx Virtex-7 FPGA.