Design solutions for the interconnection parasitic effects in deep sub-micron technologies

Abstract

Interconnection parasitic effects are one of the factors that limit the performances of deep sub-micron VLSI designs, since parasitic capacitance increases with decreasing geometrical dimensions, becoming the dominating delay contributor. Technology alone cannot offer a satisfying solution, because new materials offer only a limited reduction in parasitic effects, while introducing new reliability and manufacturability concerns. The problem must be managed at the design level, by adopting proper design and verification methodologies. However, the introduction of delay verification after layout is not enough, since, with increasing design complexity, no guarantee exists that the procedure of delay verification and layout correction will converge. Ways must be found to take care of interconnections at an early design stage, achieving a delay aware floor planning. A further source of problems, which is starting to play a significant role, is the delay introduced by cross-talk effects, which are essentially dynamic in nature. Cross-talk Aware Static Timing Analysis techniques must be introduced to identify, in a fast way, critical nets, limiting the required corrections to a small subset of the total design.