Design, simulation and implementation of a low-power digital decimation filter for G.232 standard

Abstract

A power efficient multistage digital decimation filter for an ADSL modem is presented. In this design, a fractional delay (FD) filter with complex coefficients, a symmetric FIR filter, and a shift register are used to meet the requirements of the G.232 standard. The multistage architecture of the decimation filter consumes less than 28% of power consumed by single-stage implementation for oversampling ratio of 16. Although the order of the designed filter is low (16), it provides very accurate magnitude and group delay responses within the passband.