Design, Simulation and Experimental Verification of Chip-Level Cracking Structure

Abstract

To quickly destroy chip and ensure information security, the author designed a cracking structure of transient-failure integrated circuit in this paper. By placing the Ni-Cr film resistance and the energetic material between the chip and the package and heating the resistance by an electric current, the energetic material expanded and the chip cracked. The information on the chip was destroyed, destroying the information on the chip. The author simulated the temperature distribution and stress of the power-on structure in different sizes by ANSYS software. The simulation results indicate that, the chip cracks within 50ms under the trigger current of 0.5A when a circular groove with an area of 1mm2 and depth of 0.1mm is filled with an expansion material with an expansion coefficient of 10- 5·℃-1. Then the author prepared a sample for experimental verification. Experimental results show that the sample chip quickly cracks and fails within 10ms under the trigger current of 1A. The simulation and experimental results confirm the feasibility of the structure in quick destruction, which lays the foundation for developing instantaneous-failure integrated circuit products to meet information security applications.