Design, selection and implementation of a content-addressable memory for a VLSI CMOS chip architecture

Abstract

The paper reports an investigation into the design constraints, trade-offs and implementation issues involved in the design of a large content-addressable memory (CAM) for a VLSI CMOS high-speed associative chip architecture: the single chip array processing element SCAPE associative parallel processor. It includes results from a study into determining the general electrical and physical characteristics of a range of CAM cells; details from a case study of the SCAPE chip that predicts the performance of CAMs within a VLSI-based parallel processing computer system, together with the overall impact the CAM design has on the SCAPE chip performance; the selection and implementation engineering of the most cost-effective CAM design for the SCAPE chip.