Abstract
Microprocessors continue to grow in capabilities, complexity and performance. The current generation of microprocessors integrates functional components such as logic and level two (L2) cache memory into the microprocessor architecture. The functional integration of the microprocessor has resulted in better performance of the microprocessor as the clock speed and the instruction execution time has increased. However, the integration has introduced a layer of complexity to the thermal design and management of microprocessors. As a direct result of function integration, the power map on a microprocessor is highly non-uniform and the assumption of a uniform heat flux across the chip surface is not valid. Previous work (Kaisare, 2005) has been done to minimize the thermal resistance of the package by optimizing the distribution of the nonuniform powered functional blocks with a specific power matrix. The objective of this paper is to come up with a design rule in general for functional block distribution in a nonuniformly powered microarchitecture. In order to model the nonuniform power dissipation on the silicon chip, the chip surface area is divided into different cases such as 3 times 3, 4 times 4 etc. of power matrix with a matrix space representing a distinct functional block with a constant heat flux. Finally, using a FEM code, an optimization of the positioning of the functional blocks relative to each other was carried out in order to minimize the junction temperature Tj. The best possible Tjmax reduction could thus be found. In reality (and at a later date) constraints must be placed regarding the maximum separation of any 2 (or more) functional blocks to satisfy electrical timing and compute performance requirements A design rule for minimizing thermal resistance will be developed for any number of functional blocks for a given nonuniformly powered microprocessor. The commercial finite element code ANSYSreg is used for this analysis
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