Design Oriented Analysis of Discrete-Time Current Regulator Design for Low Carrier Ratio Sensorless High-Speed Permanent Magnet Synchronous Machine Drives

Abstract

High speed permanent magnet synchronous machines (HSPMSMs) are evolving rapidly due to their high-power density, high efficiency and wide speed range. However, the rated frequency often exceeds 1kHz while the switching frequency of conventional Insulated Gate Bipolar Transistor (IGBT) is generally around 10kHz, resulting in a low carrier ratio (carrier frequency/operating frequency), even < 10 with significant control delay. This leads to severe inverter output voltage phase error, reducing the dynamic performance of the system. It also exacerbates dq-axis cross coupling, making standard current regulators ineffective. In general, low carrier ratio can degrade the performance and stability of the motor drive system. This paper investigates these issues with different design methods and current regulator configurations. The discrete-time domain HSPMSM model is developed that includes the delay effects associated with digital implementation and pulse width modulation (PWM). This model is then used to design a discrete-time domain deadbeat controller that demonstrates improved response compared with other regulators studied. Simulation and experimental results using a 380V, 14krpm HSPMSM and 9kHz switching frequency are provided to compare performance, stability, and robustness of the current regulators analyzed. It is demonstrated that the steady-state angle error is nearly zero and the error under high-speed transient dynamics is within 1°, showing good parameters robustness under ±30% stator inductance and ±50% stator resistance variations.