Design Optimization of Power and Area of Two-Stage CMOS Operational Amplifier Utilizing Chaos Grey Wolf Technique

Telugu Maddileti,Govindarajulu Salendra,Chandra Mohan

doi:10.14569/ijacsa.2020.0110760

Telugu Maddileti, Govindarajulu Salendra + Show 1 more

Open Access

https://doi.org/10.14569/ijacsa.2020.0110760

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Abstract

Low Power Dissipation is an emerging challenge in the current electronics industry. Area shrinking has found the most prominent place and is the foundation of every constricted size in the utilization of CMOS circuits in Integrated Circuit Manufacturing. Functionality in terms of rapidity, dissipation of power, etc. are strongly influenced by the dimensions of transistors in many CMOS Integrated Circuits. The significant formulation parameters in CMOS circuit design to perform optimization of the above-mentioned parameters, and various techniques were projected earlier to a maximum extent possible. Latency, Power, and Dimension are significant parameters in the design of CMOS based IC design. Most analog circuit reduction in terms of size as parameter typically describes solitary or many objectives-controlled optimization issues. The eminent challenges with regards to size and power dissipation can be described as problems that are typically encountered under certain conditions. In this study, the design of a two-stage CMOS Differential Amplifier applying the nature-inspired Grey Wolf Algorithm for optimizing the area and power is utilized. To enhance the formulation terms concerning important considerations such as the amount incurred, strength, and functionality; a computerized formulation approach is used. This formulated design proposal will meet specifications such as positive and negative Slew Rate, Unity Gain Bandwidth and Phase Margin, etc. Chaos theory can be induced into the Grey Wolf Optimization Algorithm (CGWO) with the help of speeding global convergence metric i.e. Speed. The results obtained from CGWO are then analyzed with the functionality of other prevailing optimization techniques employed in the analog circuit sizing. Depending on the investigations, CGWO functions reduce the dimensions of the circuit and analyze the prevailing techniques by achieving a healthier rate of convergence and power dissipation with low value.

Highlights

The development of expertise, compact devices, and special equipment have brought a tremendous change and enhanced an individual’s style of living
This paper described the collective benchmark circuit employments at gate level optimizing the dimensions of transistors utilizing evolution dependent GA technique
The optimal sizes of the MOS transistors along with Load Capacitance and Compensation Capacitance by minimizing the primary objectives that are power dissipation and area is performed by the proposed CGWO technique

Summary

Introduction

The development of expertise, compact devices, and special equipment have brought a tremendous change and enhanced an individual’s style of living. EDA based mechanisms support in identifying the best possible formulation techniques for reducing the power consumption adopting a strategy for reducing the dimension of gate sizing and choice of VT. Engineers spend their considerable energy concentrating on the choice of software to formulate a devising strategy that satisfies formulation challenges. In addition to attaining the power objectives in the requirement, present electronic design software available in the market functions with a certain percentage of power reduction It may not sufficiently explain the case where it originates in employing the strategy that satisfies the frequency needs utilizing reduced power in a global circumstance [13]. Gate Sizing Optimization is crucial to obtain timing closure and minimize the power dissipation of integrated circuits [12]

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