Design optimization of N-LDMOS transistor arrays for hot carrier lifetime enhancement

Abstract

Today's power management devices often require operation in the 20-30 V range. These applications combine a high performance BiCMOS process with a power lateral n-channel DMOS (N-LDMOS) driver. To obtain high drive currents and low on-resistance, LDMOS devices are often implemented in transistor arrays. Because of the high voltages and currents applied to these arrays, hot carrier (HC) degradation is a real reliability concern. This paper differs from previous work in that it discusses for the first time one- and two-dimensional aspects of LDMOS transistor array layout on HC performance and introduces a novel LDMOS transistor layout featuring a drain ring that substantially improves the array's HC performance.