Design Optimization Considering Guiding Template Feasibility and Redundant Via Insertion for Directed Self-Assembly

Abstract

While multiple patterning lithography suffers from considerable and increasing mask manufacturing cost, next generation lithography technologies are urgently required for sub-10 nm technology nodes, where directed self-assembly (DSA) is one of the most promising candidates for contact/via layer fabrication. In addition, redundant via insertion is regarded as an important step in the circuit design flow to improve circuit reliability and yield. In this paper, we propose to adopt wire perturbation to further enhance via manufacturability and redundant via insertion rates. In addition, an improved DSA-compliant and redundant via-aware routing graph model is proposed and a systematic via graph update approach is developed to facilitate the implementation of the router. Experimental results demonstrate that compared with a state-of-the-art work, our wire perturbation approach can averagely increase inserted redundant vias by 6% and reduce unmanufacturable vias by 23% with only 0.9% wirelength overhead, and our routing graph model achieves the same performance as the one proposed in a state-of-the-art work and is much more efficient.