Design Optimization and Experimental Validation of Gate Driver for 10 kV SiC MOSFET

Abstract

Medium voltage silicon carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) are advantageous in numerous industrial applications by enabling simple two-level topologies. However, medium voltage SiC MOSFET also challenges the gate driver design from the following three aspects: 1) high voltage isolation requirement for the gate driver power supply (GDPS); 2) due to the very fast switching speed or high dv/dt of the device, a low coupling capacitance for the GDPS is desired; 3) fast and reliable overcurrent protection function is required for the gate driver to protect the expensive medium voltage SiC MOSFET. In this paper, a stacked structure wireless power transfer (WPT) based GDPS is designed and optimized. The stray magnetic field is suppressed by designing the shielding layer. A two-stage gate driver structure by using commercial gate driver integrated chips (ICs) is used to provide reliable and fast overcurrent protection. The clearance requirement is satisfied on the gate driver board to avoid isolation issue. The characteristics of the designed GDPS and gate driver are experimentally investigated by using 10 kV SiC power module under 6 kV DC bus voltage condition. The equivalent coupling capacitance for the designed GDPS is around 2.5 pF and the DC voltage isolation is tested up to 20 kV. Reliable overcurrent protection function is validated under 6 kV DC bus voltage test condition.