Design, optimization, and analysis of Si and GaN nanowire FETs for 3 nm technology

Abstract

Nanowires, due to their unique properties, are emerging as the building blocks of the next-generation electronics industry and will play a critical role in both low- and high-performance circuits and systems. This work presents the design, optimization, and analysis of a silicon (Si) and gallium-nitride nanowire field-effect transistor (GaN NW FET) to evaluate its performance at the ultra-scaled device dimensions required for GaN NW FETs in the electronics industry in order to increase the packing density and overall performance of the device. The analysis was carried out using self-consistent Poisson and Schrödinger equations based on a non-equilibrium Green function (NEGF) approach using Silvaco ATLAS. A reduction of 84.07% in the ‘off’ current was observed for the GaN NW FET, as compared to its Si counterparts, which reveals the requirement for a GaN NW FET at extremely scaled dimensions for ‘off’ state leakage suppression. Optimization of the electrostatic control mechanism, gate oxide, gate oxide thickness (t ox), and metal work functions (φ ms) was performed using quantum simulation models to investigate the influence of these parameters on the device performance. A way of improving the I on/I off ratio of the device has been reported using metal contact length and width variations. A 40% reduction in the subthreshold swing value offers improvements in the electrostatic control I on/I off ratio of ∼104, ∼105, and 102 due to the respective optimizations of the metal contact length (L c), metal contact width (W c), and metal work function (φ ms) of the GaN NW FET, compared to the Si NW FET, thus making the GaN NW FET an intriguing option for digital electronics applications. A comparison of the semi-classical (Drift Diffusion_Mode Space) and quantum (Non-Equilibrium Green Function_Mode Space) transport models was also carried out to reveal the importance of the accuracy of these models at such low dimensions. This optimization and analysis will help us to further improve the performance of experimental work and will act as a reference for the same. This study reveals the performance advantages of the GaN NW FET over the Si NW FET for transistor applications in the electronics industry and can serve as a reference point for the researchers working in this area. To the best of our knowledge, no such comparison has been reported so far for Si and GaN NW FETs using 3 nm technology.