Abstract
In this paper, a novel high-speed parallel structure of low-pass filter for filtering and matched algorithm for searching synchronization in DSSS receiver is studied. We extend previous implements for introducing parallelism into the design of Direct Sequence Spread Spectrum (DSSS) receiver. Design techniques, such as parallel structure, optimized compressor cells and pipeline architecture for reducing the hardware resource consumption of multiplier , adder and look-up tables (LUT), use to realize a high-speed processing, precise synchronized and reconfigurable DSSS receiver. The design trade-offs analyzed with ISE 10.1 in detail, including the maximum frequency and number of resources of slices, bonded IOs and GCLKs, and implemented with a XC4VLX160 FPGA device.
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