Abstract
A modular hardware accelerator (MHA) is designed to provide a platform to interface with any computation algorithm (engine). The main blocks in MHA include a hardware accelerator adapter unit, scheduler unit, storage unit, power management unit, and workload generator (WG) unit. The current paper proposes a design of the WG for MHA. The WG unit will maintain the sequence of tasks that will be executed by the engine. The WG unit implements a 64-bit address bus, a 128-bit data bus, and a maximum request data length of 1024 double word to the main memory, with processing speed of 100 MHz.
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