Abstract
Frequency multipliers are key components for high quality sinusoidal signal provision in millimeter-wave systems. Suppression of unwanted harmonics is an important challenge, for regulatory reasons, but also since unwanted harmonics can negatively impact system performance. Explicit filtering of fundamental frequency and unwanted harmonics (even interstage in cascaded multipliers), comes at the expense of loss and high on-chip area consumption in IC implementations. Proper circuit topology and circuit optimization greatly alleviates filtering requirements. This will be discussed in the paper and exemplified for FMCW radar sensors at F-band.
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