Design of Viterbi decoders with in-place state metric update and hybrid traceback processing

Abstract

A novel design of Viterbi (1965) decoder based on in-place state metric update and hybrid survivor path management is presented. For those Viterbi applications with large constraint length, the proposed design methodology can result in high-speed and modular architectures by exploiting the in-place computation feature of the Viterbi algorithm. This feature is not only applied to the design of highly regular add-compare-select (ACS) units, but also exploited in the design of trace-back units for the first time. The proposed hybrid survivor path management based on the combination of register-exchange and trace-back schemes cannot only reduce the number of memory operations, but also the size of memory required. Compared with the general hybrid trace-back structure, the overhead of the register-exchange circuit in our architecture is significantly less. Therefore, the proposed architecture can find promising applications in digital communication systems where high-speed large state Viterbi decoders are desirable.