Design of Viterbi Decoder Based on FPGA

Abstract

The minimum bit width of the path metrics at the premise of not affecting the performance are calculated out, in order to reduce the storage resources cost in the design of convolutional code decoders. A simple method is proposed to judge the state nodes which the decoder can reach at each clock cycle during the setup process. Simulation platform to verify the proposed scheme has been set up with the matlab software, after that a decoder of (2,1,8) convolutional code with generating polynomial (561,753) is designed. Result of comparison with other designs shows that the scheme proposed greatly improves the throughput of the decoder at the cost of fewer resources.