Design of up/down counter based on dual mode logic and Low power Hybrid dual mode dynamic flip-flop

Abstract

This paper introduces a 4-b Johnson up-down counter that incorporates low power dual dynamic node pulsed hybrid flip-flop (DDFF) with clock gating technology and a dual mode logic (DML) in the counter. Clock gating disable the clock signal when the input data does not change the stored data. A DML mode logic is introduced here which improves the speed performance of the design, also achieving significant energy consumption reduction. The large capacitance in precharge node is eliminated by the DDFF and DDFF-ELM designs by following a split dynamic node structure. The DDFF offers power reduction. The DDFF-ELM reduces pipeline overhead. 4-b Johnson up-down counter is used to magnify the performance improvement of the designs, to which the DML logic is introduced. An area, power, and speed efficient method is presented here that incorporates complex logic functions into the flip-flop. The DML logic used in DDFF-ELM helps to achieve low power and high speed requirements. The simulation results are compared using T-Spice