Abstract
CMOS devices play a major role in most of the digital design, since CMOS devices have larger density and consume less power. The integrated circuit performance mostly depends on the basic devices and its scaling methods, but in conventional CMOS devices in ultra deep submicron technology, leakage power becomes the major portion apart of dynamic power. The demerits of the conventional CMOS is less speed and, more leakage, for any digital design PDP is the figure of merit which can be used to determine energy consumed per switching event, hence we designed a NOVEL NMOS and PMOS which has superior performance than conventional PMOS and NMOS, the design and performance checked at 90 nm, 180 nm and 45 nm technology and calculate the performance values.
Highlights
The need for low power chips is the increased marked demand for portable consumer electronics powered by the batteries, which have not experienced the similar rapid density growth compared to electronics circuits
An attempt has been made to control leakage power by proposed PMOS and NMOS, the fundamental limit of conventional PMOS and NMOS is higher leakage and lower sped in deep submicron technology sine power supply reduction lowers three times the threshold voltage will degrade the speed of the circuit considerably, as we are striving forward to higher level of integration, area is not having that much of concern, we are in position to keep millions of transistors in a single die, the other performance parameters like power, speed and delay power delay product are important parameters which can decide the role of the device in nano scale regime [5]
The PMOS and NMOS are good transfer of 1 and good transfer of 0, the comparative study is done on various types of MOS devices like PMOS, DTMOS and proposed MOS devices, the average power, delay and PDP is calculated by using the cadence virtuoso design environment tool for 45 nm, 90 nm, 180 nm technology [7]
Summary
The need for low power chips is the increased marked demand for portable consumer electronics powered by the batteries, which have not experienced the similar rapid density growth compared to electronics circuits. The different power reduction techniques from device level to circuit level and system level have been shown as a low power taxonomy [1]. In ultra-deep submicron technology especially below 45 nm technology, leakage power is becoming a major. (2015) Design of Ultra-Low Power PMOS and NMOS for Nano Scale VLSI Circuits. As the technology is going on scaling down, and we are in 20 nm/15 nm/ 10 nm technology proper controlling of leakage power is becoming challenge factor. Related work: The existing numerous power reduction techniques in the field of VLSI are suitable for only 90 nm and above, but continuous scaling of the device in the present VLSI technology many of them may not be suitable. The major source in the overall power dissipation is the dynamic power Pdynamic =α ×VD2D × CL × f. As the technology shrinks leakage power is to be dealt very carefully
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