Design of Two Interleaved Error Detection and Corrections using Hsiao Code and CRC

Abstract

A radiation-induced single-event upset (SEU) is a major disruption to electronics operating in satellites. If not rectified, a single-bit-error can become uncorrectable. In this paper, we present two interleaved Double-Adjacent-Error-Corrections (DAECs) for Error Detection and Correction (EDAC), using the Hsiao Code and Cyclic Redundancy Code (CRC). From our results, both EDACs can correct 100% of the single-bit-errors, double-adjacent-bit-errors, and detect double-bit-errors and up to four-adjacent-bit-errors. The Hsiao Code EDAC encoder design requires less bit-weight than the CRC EDAC, which is an attribute of a high-speed EDAC. The CRC EDAC, in contrast, has a higher error detection rate for both three- and four-bit-errors, at 96.25% and 91.92%, respectively. We also propose two storage formats and algorithm designs that can manage and store the 48-bit codeword in 8-bit and 16-bit memory devices, a typical satellite scenario where board space is scarce. We used Verilog HDL, C++, and ModelSim to create and test our designs.