Design of Thin-Body Double-Gated Vertical-Channel Tunneling Field-Effect Transistors for Ultralow-Power Logic Circuits

Abstract

A structure of a tunneling field-effect transistor (TFET) featuring an extremely thin body, a double-gated vertical channel, and a source design to maximize the drive current is proposed and optimized on the basis of technology computer-aided design (TCAD) simulation. The field-coupling effect at the double-gated thin-body channel and an engineered tunneling barrier are implemented to maximize the operation current of the device. Weak current drivability under a small drain bias and the directionality of current flow are the expected challenges in building logic circuits with TFETs. A co-integration scheme to build vertical-channel TFETs and metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed as the solution. A new low-power design using the co-integration scheme is suggested.