Design of the Test Architecture for IP Cores on SoC Based on IEEE 1500 Standard

Abstract

For system-on-chip (SoC) test based on IP cores integration reuse, the IEEE 1500 Standard has given specific testing architecture. In this paper, we aim at building controllable test architecture for IP cores on SoC based on IEEE 1500 Standard. The technique applied is referred to as test control switch which is configured to the Wrapper of IP cores. We design a switch control register (SCR) to configure the state of the switches, and apply the expanded TAP (eTAP) based on IEEE 1149.1 Standard to control the SCR and the Wrapper of IP cores. In addition, we design the chip level test control architecture which can be widely used for test of SoC based on IP cores. Finally, we apply the software of Modelsim to implement simulation about the control mechanism of the SCR and the eTAP. The simulation results show the effectiveness and controllability of the test architecture.